Course (Category)

Code

Course Name

Teaching Scheme (Hrs/week)

Credits Assigned

L

T

P

O

E

L

T

P

Total

MDM4

Engineering Reliable  Time Triggered Systems

3

—

2

3

8

3

—

1

4

Examination Scheme

Component

ISE (%)

MSE (%)

ESE (%)

Total

MDEC45

Theory

20

20

60

100

Laboratory

80

—

20

100

Pre-requisite Course Codes, if any.

Advanced Time-Triggered Systems Design

Course Objective: To develop the ability to create software for safety-critical systems designed according to Safety Integrity Levels (SIL) 0 to 3, using Time-Triggered Architectures, involves gaining a solid understanding of both the principles of safety-critical software engineering and the specifics of Time-Triggered systems.

Course Outcomes (CO): At the end of the course students will be able to

MDEC44.1

Understand, Apply, Create and Analyze code for Redundancy: For SIL 2 and above, you’ll need to design for redundancy (e.g., dual-channel architecture) to ensure that a failure in one channel does not result in system failure.

MDEC44.2

Understand, Apply Create and Analyze code for Fault Tolerance: Understand how Time-Triggered Architectures can provide fault tolerance through time-based checks and fault isolation.

MDEC44.3

Understand, Apply Create and Analyze code for Error Detection and Handling: Learn how to implement mechanisms such as watchdog timers, integrity checks, and redundancy management to detect and handle failures.

MDEC44.4

Understand, Apply Create and Analyze code for Diagnostic Coverage: A significant aspect of SIL certification, ensuring that the system can detect and respond to faults appropriately.

MDEC44.5

Relate and evaluate  the design for compliance with international safety standards e.g. IEC 61508, ISO 26262, DO-178C to name a few

PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9

PO10

PO11

PO12

MDEC44.1

3

3

3

3

3

3

MDEC44.2

3

3

3

3

3

3

3

MDEC44.3

3

3

3

3

3

3

MDEC44.4

3

3

3

3

3

3

MDEC44.5

3

3

3

3

3

3

3

3

3

3

3

3

Remember√

Understand√

Apply√

Analyze√

Evaluate√

Create√

Module No.

Unit No.

Topics

Ref.

Hrs.

1

Title

Introduction

1

04

1.1

A simple TTC scheduler

2

Title

Foundations of reliable systems

1

08

2.1

Polling and buffering

2.2

Data storage and data transfers

2.3

Interacting with peripherals

3

Title

Tasks and peripheral management

1

14

3.1

Interacting with peripherals

3.2

Diverse and Balanced tasks

3.3

Processor software state and Shared Clock and GALS system

4

Title

Modelling TTC designs

1

03

4.1

Modelling with tick lists

4.2

Modelling shared clock systems

5

Title

Monitoring TTC designs

1

13

5.1

Performing POST’s and BIST’s

5.2

Making use of iWDT(internal watchdog timer) and WaranTTor unit

5.3

Monitoring task execution times and Task execution sequences, Selecting MCU’s for your system

6

Self Study

Participants have to read the reference material to dig out information from the reference material and the online resources to  design the given systems as per the given specifications .

Online resources and R.3

*42

Total (*Not included)

42

Sr. No

 Title of the Experiment

1

Create a TTC scheduling mechanism:

·         Build the project with the required .c and .h files with the requisite function prototypes

·         Create the required functions for the scheduler

·         Test the scheduler with some dummy tasks with different task arrival times

2

Register Configuration checks

·         Use the scheduler created at Sr. No.1 to configure the various registers of the like the Systick timer, watchdog timer  and UART register for correct configuration.

·         Build code to use the scheduler for checking the configuration of the various registers before application start

3

Duplicated variables

·         Use the scheduler created at Sr. No.1 to create duplicate of each critical variable to verify that the configuration is not changed and is as per the requirement.

·         Write code to compare the duplicated variables with the original variables to ensure that there is no change in the values.

·         Apply this technique to check the configuration registers of used peripheral as well.

4

Mode change :Processor in abnormal state

·         Use the Scheduler at Sr. No. 1 to write code for two processor states viz:

·         Processor in normal state

·         Processor in abnormal state

·         Conduct tests to ensure that the application is run only if the processor is in normal state.

5

Buffered outputs

·         Use the Scheduler at Sr. No.1 to create output buffering.

·         Check the task times and ensure proper buffering is done at the output to ensure that task times become independent of the time it takes to send data to the output.UART could be used here.

Sr. No

Title

Edition

Authors

Publisher

Year

1

Engineering Reliable Embedded Systems

2nd

Michael J. Pont

SafeTTy Systems

2016

Sr. No

Title

Edition

Authors

Publisher

Year

1

Patterns of Time Triggered Embedded Systems

1st

Michael J. Pont

Pearson

2014

2

The C programming Language

2nd

Dennis Ritchie and Brian Kernighan

Pearson education

2015

3

MISRA C :Guidelines

–

MISRA.ORG.UK

MISRA

2012