Course (Category)

Code

Course Name

Teaching Scheme (Hrs/week)

Credits Assigned

L

T

P

O

E

L

T

P

Total

MDM3

Advanced                      Time-Triggered Systems Design

2

0

2

4

8

2

0

1

3

Examination Scheme

Component

ISE (%)

MSE (%)

ESE (%)

Total

MDEC35

Theory

20

20

60

100

Laboratory

80

—

20

100

Pre-requisite Course Codes, if any.

Foundations of Time Triggered architectures 

Course Objective:

Course Outcomes (CO): At the end of the course students will be able to

MDEC35.1

Understand about the benefits that can be obtained by developing reliable embedded systems using time-triggered (TT) architectures.

MDEC35.2

Apply TT architectures in their own designs.

MDEC35.3

Understand both the strengths and weaknesses of a Time-Triggered approach to the development of software for reliable embedded systems

MDEC35.4

Create a time triggered co-op scheduler for designing systems

MDEC35.5

Create a time triggered hybrid scheduler for designing systems

MDEC35.6

Analyze the code and test the code for all the use cases since the system designed will always be deterministic due to the inherent nature of TT architectures

MDEC35.7

Evaluate different scheduling strategies and decide which scheduling mechanism is best for the given scenario. Then apply the scheduling algorithm for the design.

PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9

PO10

PO11

PO12

MDEC35.1

3

3

MDEC35.2

3

3

3

MDEC35.3

3

MDEC35.4

3

3

MDEC35.5

3

3

2

MDEC35.6

3

3

MDEC35.7

3

Remember

Understand√

Apply√

Analyze√

Evaluate√

Create√

Module No.

Unit No.

Topics

Ref.

Hrs.

1

Title

What is a time-triggered system?

1

01

1.1

Introduction, Information systems, Desktop systems, Embedded systems, Real-time systems .

1.2

Event-triggered systems

1.3

Time-triggered systems

2

Title

Software foundations

1

04

2.1

Rudimentary software architecture, Super loop, Project header, Delays, Hardware delay, Software delay.

2.2

Watchdog, Issues and challenges of using a standard RTOS in reliable embedded systems, Priority based pre-emptive scheduling, Challenges caused by shared resources, Mutual exclusion, Priority Inversion(PI)

2.3

From Priority inversion to deadlock, Dealing with deadlock, Example of PI to deadlock, Real challenges presented by PI, Challenges with dynamic RTOS.

3

Title

Time Triggered (TT) architectures for single processor systems

1

04

3.1

An introduction to schedulers, The desktop OS, Assessing the super loop architecture, Executing multiple tasks at different time intervals

3.2

What is a scheduler?, Co-operative and pre-emptive scheduling, A closer look at pre-emptive schedulers, Task oriented design.

4

Title

Scheduler

1

17

4.1

Co-operative scheduler -TTC

4.2

Hybrid scheduler-TTH

4.3

Shared clock scheduler- SC

5

Title

Working with MISRA C (International guidelines and standard)

1

02

5.1

Vision and Objectives of MISRA C

5.2

Relationship to other guidelines

5.3

Applying MISRA C guidelines

6

Self-Study

Material in the Online resources has to be read as told by the instructor for understanding the implementation details of the peripherals.

Online resource-1 and 2 and R.2

*56

Total

28

Sr. No

Title of the Experiment

1

Repeat the early prototype of a control system for lowering an aircraft undercarriage exercise with the correct implementation of the sEOS learnt in the theory and deciding how many tasks would be needed in the system. Documenting the findings of the practical 2 and this practical w.r.t. the timing correctness and the deviation from the given specification is essential

2

Pulse Width Modulation on two different pins with different duty cycles. The system should stop after 40secs and restart when the system is reset again

3

Identify the startup file used with your μVision project for Exercise 4 and explaining how it operates.

4

There are three parts to this practical

Part a deals with creating a task having a certain BCET, ACET and WCET. Use of Super Loop architecture is required here

Part b deals with using sandwich delay architecture.

5

Part c of Laboratory 4. Use appropriate sEOS implementation to implement the system in Laboratory 4.Document the jitter level to arrive at a conclusion.

6

18 MISRA C rules will be provided. Participants need to explain the rules with help of code snippets

7

A task has to be designed that runs at a given interval and has a given WCET. This task has a transitory overrun at some given interval. Two implementations are to be done , one with sEOS and other with TTC .Using the timing measurements from the toolset, the major  observations with both the implementations has to be documented

8

A short frequent task and a long task has to be implemented using the  hybrid scheduler

9

A report which compares the advantages and disadvantages of the C and Ada programming languages from the perspective of a company which develops reliable embedded systems.  This report should compare MISRA C and SPARK ADA and also mention what impact would you expect these subsets to have on system reliability?

10

A report has to be written  relating the D0-178C aerospace guidelines investigating the impact on a software company following these guidelines

Sr. No

Title

Edition

Authors

Publisher

Year

1

Patterns of Time Triggered Embedded Systems

1st

Michael J.Pont

Pearson

2014

Sr. No

Title

Edition

Authors

Publisher

Year

1

The C programming Language

2nd

Dennis Ritchie and Brian Kernighan

Pearson education

2015

2

MISRA C :Guidelines

–

MISRA.ORG.UK

MISRA

2012